1. Field of the Invention
The present invention relates to logic gates generally and, more particularly, to logic gates integratable with III-V technologies such as in Gallium Arsenide (GaAs) integrated circuits.
2. Description of the Prior Art
Gallium Arsenide has long been recognized as material which could be used to integrate high-speed logic circuitry. However, due to inherent manufacturing difficulties associated with this kind of material, conventional logic circuits, i.e. those designed for integration into silicon, are not readily adaptable for integration into GaAs or other III-V materials such as Indium Phosphide. Consequently, several types of digital logic families were developed for use in GaAs integrated circuits. Exemplary common logic families are Buffered FET Logic (BFL), Direct Coupled FET Logic (DCFL), Schottky Diode FET Logic (SDFL) and Source-coupled FET Logic (SCFL). Each family is for the most part incompatible due to different logic voltage levels employed by each. Further, power dissipation, noise margins and propagation delay per gate varies widely from family to family. For example, BFL requires two bias voltages and suffers from high power dissipation. DCFL is a fast, relatively low power logic family but has small logic level voltage swings (typically 0.6 volts), resulting in small noise margins. SDFL is somewhat slower than DCFL but with better noise margins and higher power dissipation than DCFL. SCFL logic suffers from high power dissipation while providing high speed and large fan-out. These and other logic families are discussed in more detail in "GaAs Devices and Circuits", by Michael Shur, Plenum Press, 1987, pp. 434-449.
In Very Large Scale Integrated Circuits (VLSI) where many thousands of logic gates are utilized on a single wafer, the power dissipation of a logic gate becomes a major concern while still providing high speed. For example, the number of gates on a silicon VLSI chip using emitter-coupled logic is usually limited by the power dissipation of the chip. Consequently, for a GaAs VLSI chip, the most frequently utilized logic family is DCFL due to the relatively low power dissipation per DCFL gate. However, the small noise margins of DCFL, typically 0.2 volts, and small logic level voltage swings, typically 0.6 volts, greatly limits chip yield from a wafer. Wide variations in FET characteristics (parametrics) across a wafer, even across each chip, result in threshold voltage variations for the DCFL gates which significantly reduce, even eliminate, the noise margins. This, combined with the large amounts of electrical noise generated by the gates changing state, can disrupt operation of VLSI circuit designs. Hence, the limitation on the number of gates per GaAs chip using DCFL is limited not by power dissipation but by the desired chip yield of operable chips per wafer.
Therefore it is a primary object of this invention to provide a new logic family having high speed and low power dissipation compatible with large scale integration in III-V materials, such as Gallium Arsenide or Indium Phosphide.
A further object of the invention is to provide a logic family tolerant of device parametric variation with wide noise margins for use in high density VLSI chips and gate arrays without sacrificing speed or power dissipation.